1. Field of the Invention
This invention relates generally to decoder circuits for the selection of storage devices in memory arrays. More specifically, it relates to loop decoder circuits which utilize Josephson junctions and superconducting loops which can be utilized in conjunction with bit-oriented memory arrays which incorporate Josephson junction memory cells. Still more specifically, it relates to decoder circuits which utilize serially disposed address devices which, in turn, control current flow in a plurality of superconducting loops each of which contains current steering circuits, the outputs of which control the actuation of 2.sup.N similar circuits associated with a pair of loops of a succeeding (N+1) stage. Still more specifically, it relates to a decoder circuit which utilizes a plurality of serially disposed loops each branch of which contains 2.sup.N /2 circuits similar to a serially disposed first stage circuit which includes an actuable device shunted by an impedance connected across the device by a transmission line. The transmission line contains a pair of output portions one of which controls an actuable device of a similar circuit in each branch of a succeeding serially disposed loop. Each branch of each loop contains a serially disposed address device. Thus, each loop provides 2.sup.N outputs which actuate 2.sup.N+1 actuable devices in 2.sup.N+1 circuits of a succeeding stage. The resulting decoder circuits provide advantages which include improved decoding time, improved density and improved margins over known decoders.
2. Description of the Prior Art
Tree decoders are well-known in the prior art. One such decoder is shown in FIG. 6 of U.S. Pat. No. 3,626,391, filed July 15, 1968 in the name of W. Anacker and assigned to the same assignee as the assignee of the present invention. These arrangements incorporate current steering and serially disposed actuable devices controlled by address lines block various paths so that a path is established to only one of a plurality of outputs to which current is directed.
Another decoder arrangement is shown in IBM Technical Disclosure Bulletin, Vol. 17, No. 1, June 1974, p. 280 in an article entitled "Matrix Decoder" by W. Anacker et al. In this arrangement, one out of a plurality of array lines is selected by simultaneously providing gate current to one group out of a plurality of groups of devices simultaneously with control lines each of which connects to a different actuable device in each of the plurality of groups. The application of a gate current selects one of the plurality of groups while the simultaneous application of a control current selects one device out of the selected group. Current then flows in the array line associated with the device that was actuated by the simultaneous application of gate and control currents.